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INTEGRATED CIRCUITS
DATA SHEET
TDA8742; TDA8742H Satellite sound circuit with noise reduction
Product specification Supersedes data of November 1992 File under Integrated Circuits, IC02 October 1994
Philips Semiconductors
Philips Semiconductors
Product specification
Satellite sound circuit with noise reduction
FEATURES * Demodulation of main audio signal using wide band PLL (lock range selectable) * HF input selection: two-out-of-eight secondary audio signals can be selected * Demodulation of secondary audio signals using wide band PLL * Noise reduction of the secondary audio signals * Output selection: stereo, language 1, language 2, main audio and external * Mute control * Line outputs (SCART level). QUICK REFERENCE DATA SYMBOL Supply VP VIN3(rms) fOM supply voltage PARAMETER APPLICATIONS * Satellite receivers * TV sets * Video recorders.
TDA8742; TDA8742H
GENERAL DESCRIPTION The TDA8742; TDA8742H is a multi-function sound IC for use in satellite receivers, television sets and video recorders. The pin numbers given in parenthesis throughout this document refer to the QFP44 package.
CONDITIONS
MIN.
TYP.
MAX.
UNIT
8 S/N(A) = 40 dB - 5.5 10.0 -9 A-weighted 62
12
13.2
V
Main channel input sensitivity pin 18 (14) (RMS value) lock range PLL demodulator either or VOM S/N(A) output voltage pin 23 (19) signal-to-noise ratio - - -6 70 7.5 11.5 -4 - MHz MHz dBV dB 1.0 2.0 mV
Secondary channels VIN1,IN2(rms) input sensitivity pins 2, 4, 6, 8, 10, 12, 14 and 16 (1, 3, 5, 7, 9, 11, 40 and 42) (RMS value) fOS1,2 VOR,OL S/N(A) Crosstalk S/M M/S S/S crosstalk from secondary to main channel crosstalk from main to secondary channel crosstalk between secondary channels - - - 74 74 74 - - - dB dB dB lock range PLL demodulators output voltage pins 24 and 25 (20 and 21) signal-to-noise ratio A-weighted S/N(A) = 40 dB - 10.0 -8 72 0.8 - -6 80 1.5 11.5 -4 - mV MHz dBV dB
October 1994
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Philips Semiconductors
Product specification
Satellite sound circuit with noise reduction
ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA8742 TDA8742H Note SDIP42 QFP44(1) DESCRIPTION
TDA8742; TDA8742H
VERSION SOT270-1 SOT307-2
plastic shrink dual in-line package; 42 leads (600 mil) plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
1. When using IR reflow soldering it is recommended that the Drypack instructions in the "Quality Reference Handbook" (order number 9398 510 63011) are followed. BLOCK DIAGRAM
The pin numbers in parenthesis refer to the QFP44 package.
Fig.1 Block diagram.
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Philips Semiconductors
Product specification
Satellite sound circuit with noise reduction
PINNING SYMBOL n.c. IN-1A Isel 1 IN-1B Isel 2 IN-1C MCS IN-1D HFGND IN-2A SCD IN-2B MUTE IN-2C Osel L IN-2D Osel R IN-3 VREF CD M CC M VP OM OR OL EXT/INT EXTR EXTL CATT/REC R RECTR CNR D R CD R CC R AFGND CC L CD L CNR D L RECTL CATT/REC L October 1994 PIN SDIP42 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 PIN QFP44 39 40 41 42 43 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 not connected intercarrier input A for Channel 1 (left) input select switch bit 1 intercarrier input B for Channel 1 (left) input select switch bit 2 intercarrier input C for Channel 1 (left)
TDA8742; TDA8742H
DESCRIPTION
main channel PLL lock-in range select/disable intercarrier input D for Channel 1 (left) ground for HF section intercarrier input A for Channel 2 (right) secondary channels PLLs disable intercarrier input B for Channel 2 (right) mute switch intercarrier input C for Channel 2 (right) output select switch bit 1 (left) intercarrier input D for Channel 2 (right) output select switch bit 2 (right) intercarrier input for main channel decoupling capacitor for reference voltage de-emphasis capacitor for main channel audio pass-through capacitor input for main channel positive supply voltage main channel output right channel output left channel output output switch bit 3 (external/internal) external audio input (right) external audio input (left) attack/recovery capacitor (right) rectifier DC decoupling (right) noise reduction de-emphasis capacitor (right) fixed de-emphasis capacitor (right) audio pass-through capacitor input for right channel ground for AF section audio pass-through capacitor input for left channel fixed de-emphasis capacitor (left) noise reduction de-emphasis capacitor (left) rectifier DC decoupling (left) attack/recovery capacitor (left) 4
Philips Semiconductors
Product specification
Satellite sound circuit with noise reduction
TDA8742; TDA8742H
SYMBOL CDC L CDC M CDC R n.c. n.c.
PIN SDIP42 40 41 42 - -
PIN QFP44 36 37 38 12 44
DESCRIPTION DC decoupling capacitor (left) DC decoupling capacitor (main) DC decoupling capacitor (right) not connected not connected
Fig.2 Pin configuration (SDIP42).
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Philips Semiconductors
Product specification
Satellite sound circuit with noise reduction
TDA8742; TDA8742H
Fig.3 Pin configuration (QFP44).
October 1994
6
Philips Semiconductors
Product specification
Satellite sound circuit with noise reduction
FUNCTIONAL DESCRIPTION Satellite sound The baseband signal coming from a satellite tuner contains the demodulated video signal plus a number of sound carriers to facilitate reception of a PAL/NTSC/SECAM satellite signal. Nearest to the video signal is the main sound carrier which carries the single channel sound related to the video. This is an FM modulated carrier with a fixed pre-emphasis. The carrier frequency can be in the range of 5.8 to 6.8 MHz. Additionally, a number of optional secondary sound carriers may be present which can be used for stereo or multi-language sound related to the video, or for unrelated radio sound. These carriers are also FM modulated, but for better sound quality (improved signal-to-noise performance) broadcast satellites (e.g. `ASTRA') use a noise reduction system (adaptive pre-emphasis circuit, combined with a fixed pre-emphasis). These secondary carrier frequencies can be in the range of 6.30 to 8.28 MHz. The TDA8742; H contains all circuitry for processing the main channel and for two secondary channels, from baseband signal to line (SCART) output drivers. The desired frequencies can be routed to the device via bandpass filters. Main channel (see Fig.1) The lock-in range of the main channel PLL can be switched between 5.5 to 7.5 MHz, PLL off and 10.0 to 11.5 MHz using the MCS signal at pin 7 (2) [when pin 7 (2) is at logic 0, being a voltage from 0 to 1.2 V, the lock-in range = 5.5 to 7.5 MHz; when pin 7 (2) is at logic 1, being a voltage from 3.5 V until VP, the lock-in range = 10.0 to 11.5 MHz; when pin 7 (2) is in the mid voltage position, being a voltage from 1.8 to 2.8 V, the main channel PLL is switched off]. The voltage is then determined by the resistor divider at this pin between VP and ground. If only one fixed carrier frequency for the main channel is to be demodulated (e.g. 6.5 MHz), the lock-in range of the PLL should be switched to 5.5 to 7.5 MHz. The baseband signal is applied to the main channel input, pin 18 (14) via a 6.5 MHz ceramic bandpass filter. Alternatively, if there is a requirement to demodulate different main channel frequencies, these frequencies can be transferred to a fixed intermediate frequency (e.g. 10.7 MHz) using an external mixer and oscillator-frequency synthesizer. In this event the lock-in range of the PLL should be switched to 10.0 to 11.5 MHz. The IF signal is applied to the main
TDA8742; TDA8742H
channel input, pin 18 (14) via a 10.7 MHz ceramic bandpass filter. The filtered signal is AC-coupled to a limiter/amplifier and then to a PLL demodulator. The PLL FM demodulator ensures that the demodulator is alignment-free. High gain and DC error signals from the PLL, which are superimposed on the demodulator output, require DC decoupling. A buffer amplifier is used to amplify the signal to the same level as the secondary channels and decouples DC using an electrolytic capacitor connected to pin 41 (37). The demodulator output signal is fed to pin 20 (16) via an internal resistor. The output signal can be de-emphasized by means of this resistor and an external capacitor connected to ground. Capacitor value = de-emphasis time constant per1500 (for 50 s: 33 nF). From here the signal is fed to the output selectors. The signal is amplified to 500 mV (RMS) (i.e. -6 dBV) in the output amplifiers. Secondary channels Up to eight secondary channels are available at pins 2, 4, 6, 8, 10, 12, 14 and 16 (1, 3, 5, 7, 9, 11, 40 and 42). External ceramic bandpass filters, tuned to the required secondary sound carrier frequencies, route these signals to the inputs. This enables the demodulation of eight different channel; frequencies, which are derived from the baseband, by using an external mixer and oscillator frequency synthesizer. For stereo applications the TDA8742; TDA8742H contains two identical secondary sound processing channels. For each channel it is possible to select from four inputs (IN-A, IN-B, IN-C and IN-D) using the input selector (see Table 1). With the input switch several stereo signals or languages can be selected for demodulation. It should be noted that the inputs are identical and can be freely interchanged Secondary Channel 1 will also be referred to as `LEFT' or `LANGUAGE 1' and secondary Channel 2 will also be referred to as `RIGHT' or `LANGUAGE 2'. From the input selector switch the signals are coupled to limiter/amplifiers and then to the PLL demodulators. Processing is similar to the main channel. The demodulator output signal is amplified in a buffer amplifier and DC decoupled using electrolytic capacitors connected to pins 40 (36) (left) and 42 (38) (right). The output level is set with a 220 resistor connected in series with the capacitor.
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Philips Semiconductors
Product specification
Satellite sound circuit with noise reduction
High frequency components in the amplified PLL output signal are filtered out in the audio LPF block (4th order Butterworth low-pass filter) to prevent unwanted influence on the noise reduction. NOISE REDUCTION (NR) The noise reduction can be regarded as an input level-dependent low-pass filter (adaptive de-emphasis system) followed by a fixed de-emphasis. With maximum input level (0 dB) the frequency response of the first part (i.e. without the fixed de-emphasis) is virtually flat. As the input level is lowered by x-dB, the higher output frequencies will be reduced an extra x-dB with respect to the lower frequencies (1 : 2 expansion). The NR output signal is fed to pin 36 (32) (left) and pin 32 (28) (right) via an internal resistor. Fixed de-emphasis is achieved by these resistors and external capacitors connected to ground. The signals are DC decoupled via pins 36/35 (32/31) and 32/33 (28/29) and then routed to the output selectors. OUTPUT SELECTION With the output selector (see Table 2) the outputs at pins 25 and 24 (21 and 20) can be switched to the different channels. Both outputs can be switched to both secondary channels, to the main channel and to the external inputs at pin 28 and 27 (24 and 23) for IC chaining purposes. Pin 23 (19) is a separate output which delivers the main channel only, thereby creating the possibility of having three different output channels simultaneously e.g. for use in hi-fi VCRs. The outputs at pins 25 and 24 (21 and 20) can be muted by setting the MUTE signal at pin 13 (8) to logic 1 (switch positions 6 and 7). The output at pin 23(19) can be muted by setting the MUTE signal and the EXT/INT signal at pin 26 (22) both logic 1 (switch position 7). All outputs at pins 23, 24 and 25 (19, 20 and 21) are line drivers with SCART level capability and are short-circuit protected by 125 output resistors. Output level of all channels = -6 dBV typical when frequency deviation of FM signal is 54% of maximum frequency deviation (i.e. 0.54 x 85 kHz = 46 kHz for the main channel and 0.54 x 50 kHz = 27 kHz for the secondary channels) at 1 kHz modulation frequency (reference level). ABBREVIATIONS
TDA8742; TDA8742H
fMOD = modulating frequency. fM = frequency deviation of the main Channel. fS1 = frequency deviation of secondary Channel 1 (left). fS2 = frequency deviation of secondary Channel 2 (right). fOM = carrier frequency of main Channel. fOS1 = carrier frequency of secondary Channel 1. fOS2 = carrier frequency of secondary Channel 2. LPF = Low-Pass Filter. NR = Noise Reduction. PLL = Phase-Locked-Loop.
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Philips Semiconductors
Product specification
Satellite sound circuit with noise reduction
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VP Vn Vn supply voltage PARAMETER CONDITIONS note 1 0 0 0
TDA8742; TDA8742H
MIN. 1 9
MAX. 13.2 V V V
UNIT
voltage level on pins 2, 4, 6, 8, 10, 12, 14 and note 2 16 (1, 3, 5, 7, 9, 11, 40 and 42) voltage on pins 3, 5, 11, 13, 15, 17, 20, 21, 23 to 26, 31, 33, 35, 37, 40, 41, and 42 (6, 8, 10, 13, 16, 17, 19, 20 to 22, 27, 29, 31, 33, 36, 37, 38, 41 and 43) note 2
Vn Tstg Tamb Notes
voltage on pins 7, 18, 19, 27 to 30, 32, 36, 38 note 1 and 39 (2, 14, 15, 23 to 26, 28, 32, 34 and 35) storage temperature operating ambient temperature
0 -55 -20
VP +150 +70
V C C
1. All voltages referenced to ground pins 9 and 34 (4 and 30). 2. All voltages referenced to ground pins 9 and 34 (4 and 30). These voltages must not exceed VP or maximum value at any time. THERMAL CHARACTERISTICS SYMBOL Rth j-a SDIP42 QFP44 PARAMETER thermal resistance from junction to ambient in free air 53 69 K/W K/W VALUE UNIT
DC CHARACTERISTICS All voltages referenced to ground at pins 9 and 34 (4 and 30). Measured in test circuit Fig.4; VP = 12 V; Tamb = 25 C; fM = fS1 = fS2 = 0 kHz (no modulation); fOM = 6.5 MHz; fOS1 = 10.52 MHz; fOS2 = 10.7 MHz; HF level at pin 18 (14): 40 mV (RMS); HF level at selected secondary inputs: 20 mV (RMS); MCS = logic 0 [V7 (V2) = 0 V]; SCD = logic 0 [V11 (V6) = 0 V]; unless otherwise specified. SYMBOL VP IP Ptot Vn VREF Vn VCDCL,CDCR VCDCM IIN3 supply voltage supply current total power dissipation voltage on pins 20, 21, 23, 24, 25, 27, 28, 30, 32, 33, 35, 36 and 38 (16, 17, 19, 20, 21, 23, 24, 26, 28, 29, 31, 32 and 34) input reference voltage on pin 19 (15) voltage on pins 2, 4, 6, 8, 10, 12, 14 and 16 (1, 3, 5, 7, 9, 11, 40 and 42) voltage on pins 40 and 42 (36 and 38) voltage on pin 41 (37) input current at pin 18 (14) PARAMETER - - - 3.7 - - - - MIN. 8.0 TYP. 12 38 - 3.8 3.8 0 2.7 2.8 - MAX. 13.2 45 600 - 3.9 - - - 1 V mA mW V V V V V A UNIT
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Philips Semiconductors
Product specification
Satellite sound circuit with noise reduction
TDA8742; TDA8742H
AC CHARACTERISTICS All voltages referenced to ground at pins 9 and 34 (4 and 30). Measured in test circuit Fig.4; VP = 12 V; Tamb = 25 C; fMOD = 1 kHz; fOM = 6.5 MHz; fM = 46 kHz; fS1 = fS2 = 27 kHz (reference levels); fOS1 = 10.52 MHz; fOS2 = 10.7 MHz; HF level at pin 18 (14): 40 mV (RMS); HF level at selected secondary inputs: 20 mV (RMS); MCS = logic 0 [V7 (V2) = 0 V]; SCD = logic 0 [V11 (V6) = 0 V]; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. - - - - MCS = logic 1 fOM RCDM VCDM VCDM RCCM lock range of PLL output resistance for 50 s de-emphasis pin 20 (16) output voltage pin 20 (16) spread of PLL output voltage over lock range pin 20 (16) input resistance of output amplifier pin 21 (17) note 1 MCS = logic 1; note 1 - 5.5 10.0 1.24 TYP. MAX. UNIT
Main channel - HF input pin 18 (14) and limiter VIN3(rms) VIN3(rms) RIN3 fCCO input sensitivity (RMS value) input signal level (RMS value) input resistance S/N(A) = 40 dB 1.0 - 15 2.0 200 - - - 7.5 11.5 1.7 mV mV k
Main channel - PLL FM demodulator and DC decoupling amplifier free-running frequency 6.5 10.7 - - 1.5 MHz MHz MHz MHz k
-18.5 -16.0 -14.5 dBV - 95 - 150 1 200 dB k
Main channel - overall performance (output selector in position 4) VOM,OR,OL UBM THD S/N(A) V OM ( 15 kHz ) -----------------------------V OM ( 1 kHz ) ROM,OR,OL S/M MUTEatt SVRR output voltage pins 23, 24 and 25 (19, 20 and 21) unbalance voltage outputs pins 23 to 25 (19 to 21) total harmonic distortion signal-to-noise ratio 15 kHz frequency response with respect to 1 kHz pin 23 (19) output resistance pins 23, 24 and 25 (19, 20 and 21) crosstalk attenuation from secondary channels to main mute attenuation supply voltage ripple rejection note 2 output selector in position 7 all PLLs locked output selector in position 4 all PLLs locked A-weighted; all PLLs locked no de-emphasis connected -9 -0.5 - 62 -0.5 -6 - 0.1 70 0 -4 +0.5 0.5 - +0.5 dBV dB % dB dB
92 - 74
125 74 - 35
150 - - -
dB dB dB
VRR = 100 mV; fi = 70 Hz -
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Philips Semiconductors
Product specification
Satellite sound circuit with noise reduction
TDA8742; TDA8742H
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Secondary channels 1 and 2 - HF inputs pins 2, 4, 6, 8, 10, 12, 14 and 16 (1, 3, 5, 7, 9, 11, 40 and 42) and limiters VIN1,IN2(rms) Vi(rms) Ri fCCO1 fCCO2 fOS1/2 RS1, S2 input sensitivity (RMS value) input signal level (RMS value) input resistance S/N(A) = 40 dB - - 260 - - note 3 10 0 0.8 - 330 1.5 200 380 - 11.5 2.2 mV mV
Secondary channels 1 and 2 - PLL FM demodulators (input selector in position 1) free running frequency PLL1 free running frequency PLL2 lock range of PLLs series resistance for optimum frequency response adjustment 10.7 - 0.68 MHz MHz MHz k 10.52 -
VCDCL,CDCR(rms) VCDCL,CDCR
PLL output voltage pins 40 and pins to be left open-circuit - 42 (36 and 38) (RMS value) spread of PLL output voltage over lock range output resistance for 75 s de-emphasis pins 36 and 32 (32 and 28) input resistance of output amplifiers pins 35 and 33 (31 and 29) output voltage level pins 25 and 24 (21 and 20) unbalance voltage outputs pins 25 and 24 (21 and 20) total harmonic distortion signal-to-noise ratio output resistance pins 25 and 24 (21 and 20) mute attenuation crosstalk attenuation between secondary channels note 4 note 4 note 4 A-weighted; note 4 note 4 output selector in position 6; note 4 note 5 -
9 -
- 1
mV dB
Secondary channels - overall performance of LPF and NR (output selectors in position 1) Ro 1.9 2.3 2.6 k
Ri
95
150
200
k
VOL,OR UBS THD S/N(A) Ro MUTEatt S/S M/S Voffset(DC)
-8 -1 - 72 92 74 - - 14
-6 - 0.1 80 125 - 74 74 16
-4 +1 0.5 - 150 - - - 20
dBV dB % dB dB dB dB mV
crosstalk attenuation from main note 6 channel to secondary DC offset voltage on attack/recovery capacitors pins 29, 39 (25, 35) supply voltage ripple rejection all PLLs locked; f = 0
SVRR
VRR = 100 mV; fi = 70 Hz
-
25
-
dB
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Philips Semiconductors
Product specification
Satellite sound circuit with noise reduction
TDA8742; TDA8742H
SYMBOL
PARAMETER
CONDITIONS
MIN. -25
TYP. -16
MAX. -9
UNIT
Secondary channels - low-pass filter pins 38 and 30 (34 and 26) V RECTL, RECTR ( 50 kHz ) ---------------------------------------------------------V RECTL, RECTR ( 1 kHz ) 50 kHz frequency response with respect to 1 kHz note 7 dB
Secondary channels - noise reduction pins 25 and 24 (21 and 20); note 4 VOL, OR output voltage at 0 dB noise reduction input level 15 kHz frequency response with respect to 1 kHz at 0 dB noise reduction input level output voltage at -20 dB noise reduction input level fS1 = fS2 = 50 kHz; no fixed de-emphasis connected fS1 = fS2 = 50 kHz; no fixed de-emphasis connected fS1 = fS2 = 5 kHz; no fixed de-emphasis connected -1 +1 +3 dBV
V OL, OR ( 15 kHz ) --------------------------------------V OL, OR ( 1 kHz ) VOL,OR
-2
0
+2
dB
-29
-26
-23
dBV
V OL, OR ( 15 kHz ) --------------------------------------V OL, OR ( 1 kHz )
15 kHz frequency response fS1 = fS2 = 5 kHz; with respect to 1 kHz at -20 dB no fixed de-emphasis connected noise reduction input level
-13
-11.5
-10
dB
External inputs - pin 28 (24) (left) and pin 27 (23) (right) - overall performance (output selector in position 5) VEXTR,EXTL Ri VOL,OR THD S/N(A) L/R,R/L input signal level input resistance output level total harmonic distortion signal-to-noise ratio crosstalk VEXTR, EXTL = -6 dBV VEXTR, EXTL = -6 dBV; fi = 1 kHz A-weighted; VEXTR, EXTL = -6 dBV fi = 1 kHz - 95 -6.5 - 80 - - 150 -6.0 - - 80 6 200 -5.5 0.1 - - dBV k dBV % dB dB
Input selector control circuit pins 3 and 5 (41 and 43) (see also Table 1) and secondary channels PLLs disable [SCD pin 11 (6)]; pin 11 (6); pins left open-circuit = logic HIGH VIL VIH Ri LOW level input voltage HIGH level input voltage input resistance connected to VP 0 3.5 65 - - 100 1.2 9 130 V V k
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Philips Semiconductors
Product specification
Satellite sound circuit with noise reduction
TDA8742; TDA8742H
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Output selector control circuit (see also Table 2) and main channel PLL lock-in select [MCS pin 7 (2)]; pins 15, 17, 26, 13 and 7 (10, 13, 22, 8 and 2) MOS inputs and should not be left open-circuit VIL VIM VIMF VIH RIL RIH IIL IIH Notes 1. At pin 20 (16) the demodulated 1 kHz signal should be present with a typical level of 158 mV (RMS) (-16 dBV), and THD of maximum 0.5%; VP = 8 to 3.2 V; Tamb = -20 to +70 C. 2. Modulation of main channel is OFF; modulation of secondary channels is ON. 3. The electrolytic capacitors at pins 40 and 42 (36 and 38) are removed and 1500 pF capacitors between pin 40 (36) and ground and between pin 42 (38) and ground are connected. At pins 40 and 42 (36 and 38) the demodulated 1 kHz signals should be present with typical levels of 9 mV (RMS) and THD of maximum 0.5%; VP = 8 to 3.2 V; Tamb = -20 to +70 C. 4. All PLLs locked; RS1 = RS2 = 0.68 k. 5. Modulation of secondary channel being measured and main channel is OFF; modulation of other secondary channel is ON. 6. Modulation of main channel is ON; modulation of secondary channels is OFF. 7. Measured at pins 38 (34) (left) and 30 (26) (right) and no electrolytic capacitors connected to these pins. LOW level input voltage limits MID level input voltage limits for MCS pin only MID level input voltage on MCS pin if MCS pin is floating HIGH level input voltage limits low input resistance MCS pin to ground high input resistance MCS pin to VP LOW level input current (not MCS pin) HIGH level input current (not MCS pin) VIL = 0 V VIH = 5 V VP must be 1.8 to 13.2 V 0 1.8 17 3.5 12 52 - - - - 19 - 19 80 <-1 <1 1.2 2.8 21 VP 26 108 - - V V %VP V k k A A
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Philips Semiconductors
Product specification
Satellite sound circuit with noise reduction
Table 1 Truth table for input selection STATE pins 2 and 10; IN-A (pins 40 and 5) pins 4 and 12; IN-B (pins 42 and 7) pins 6 and 14; IN-C (pins 1 and 9) pins 8 and 16; IN-D (pins 3 and 12
TDA8742; TDA8742H
SWITCH POSITION 1 2 3 4 Table 2
PIN 3 (41) 0 0 1 1
PIN 5 (43) 0 1 0 1
Truth table for output selection (note 1) PIN 15 (10) STATE OUTSEL L stereo left right main external mute secondary mute all 1 1 0 0 X X X OUTSEL R 1 0 1 0 X X X EXT/INT 0 0 0 0 1 0 1 MUTE 0 0 0 0 0 1 1 PIN 17 (13) PIN 26 (22) PIN 13 (8)
SWITCH POSITION 1 2 3 4 5 6 7 Note 1. X = don't care.
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Philips Semiconductors
Product specification
Satellite sound circuit with noise reduction
TDA8742; TDA8742H
October 1994
15
The pin numbers in parenthesis refer to the QFP44 package.
Fig.4 Test circuit.
Philips Semiconductors
Product specification
Satellite sound circuit with noise reduction
APPLICATION INFORMATION General This application is mainly intended to have more than two inputs for secondary channel available. In this event a choice between the same frequency sets e.g. 10.7 and 10.52 MHz but with different bandwidths is possible. A narrow bandwidth can be chosen in the event of a weak signal, however this produces slightly more distortion. A normal signal will be processed using 150 kHz filters thus resulting in a signal with normal distortion. For the main channel either baseband or synthesized signal can be selected. The circuit is illustrated in Fig.5.
TDA8742; TDA8742H
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Philips Semiconductors
Product specification
Satellite sound circuit with noise reduction
TDA8742; TDA8742H
October 1994
17
The pin numbers in parenthesis refer to the QFP44 package.
Fig.5 Application diagram.
Philips Semiconductors
Product specification
Satellite sound circuit with noise reduction
PACKAGE OUTLINES
TDA8742; TDA8742H
handbook, full pagewidth
seating plane
39.0 38.4 4.57 5.08 max max
15.80 15.24
3.2 2.9
0.51 min 1.73 max 1.778 (40x) 1.3 max 0.53 max 0.18 M 0.32 max 15.24 17.15 15.90
42
22
MSA268 - 1
14.1 13.7
1
21
Dimensions in mm.
Fig.6 Plastic shrink dual in-line package; 42 leads (600 mil); SDIP42; SOT270-1.
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Philips Semiconductors
Product specification
Satellite sound circuit with noise reduction
TDA8742; TDA8742H
handbook, full pagewidth
seating plane
0.1 S
S
12.9 12.3 44 1 34 33 1.2 (4x) 0.8 B
pin 1 index 0.8
11 12 0.40 0.20 10.1 9.9 22
23
0.40 0.20
0.15 M A
1.2 (4x) 0.8
0.15 M B
10.1 9.9
12.9 12.3
X
0.8
A
0.85 0.75 1.85 1.65 0.25 0.05 0.25 0.14 2.10 1.70
MBB944 - 2
detail X
0.95 0.55
0 to 10 o
Dimensions in mm.
Fig.7 Plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm (QFP44; SOT307-2). October 1994 19
Philips Semiconductors
Product specification
Satellite sound circuit with noise reduction
SOLDERING Plastic dual in-line packages BY DIP OR WAVE The maximum permissible temperature of the solder is 260 C; this temperature must not be in contact with the joint for more than 5 s. The total contact time of successive solder waves must not exceed 5 s. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified storage maximum. If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. REPAIRING SOLDERED JOINTS Apply the soldering iron below the seating plane (or not more than 2 mm above it). If its temperature is below 300 C, it must not be in contact for more than 10 s; if between 300 and 400 C, for not more than 5 s. Plastic quad flat packages BY WAVE During placement and before soldering, the component must be fixed with a droplet of adhesive. After curing the adhesive, the component can be soldered. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder bath is 10 s, if allowed to cool to less than 150 C within 6 s. Typical dwell time is 4 s at 250 C. A modified wave soldering technique is recommended using two solder waves (dual-wave), in which a turbulent wave with high upward pressure is followed by a smooth laminar wave. Using a mildly-activated flux eliminates the need for removal of corrosive residues in most applications.
TDA8742; TDA8742H
BY SOLDER PASTE REFLOW Reflow soldering requires the solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the substrate by screen printing, stencilling or pressure-syringe dispensing before device placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt, infrared, and vapour-phase reflow. Dwell times vary between 50 and 300 s according to method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 min at 45 C. REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING
IRON OR PULSE-HEATED SOLDER TOOL)
Fix the component by first soldering two, diagonally opposite, end pins. Apply the heating tool to the flat part of the pin only. Contact time must be limited to 10 s at up to 300 C. When using proper tools, all other pins can be soldered in one operation within 2 to 5 s at between 270 and 320 C. (Pulse-heated soldering is not recommended for SO packages.) For pulse-heated solder tool (resistance) soldering of VSO packages, solder is applied to the substrate by dipping or by an extra thick tin/lead plating before package placement.
October 1994
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Philips Semiconductors
Product specification
Satellite sound circuit with noise reduction
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA8742; TDA8742H
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
October 1994
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